FIG. 1 illustrates in schematic diagram form, prior art cascode differential amplifier 10. Cascode differential amplifier 10 includes P-channel transistors 12-15, 22, and 23, N-channel transistors 16-19, and current source 21. Cascode differential amplifier 10 has two symmetrical halves. The first symmetrical half includes P-channel transistors 12, 13, and 22, and N-channel transistors 16 and 17. The second symmetrical half includes P-channel transistors 14, 15, and 23, and N-channel transistors 18 and 19. In the first symmetrical half, P-channel transistor 22 has a source connected to relatively constant current source 21, and receives an input signal labeled "V.sub.INP ". A drain of P-channel transistor 22 is connected between N-channel transistors 16 and 17 at internal node 103. P-channel transistors 12 and 13 are series connected, and receive bias voltages labeled "P.sub.B1 " and "P.sub.B2 ", respectively. Cascode connected N-channel transistors 16 and 17 received bias voltages labeled "N.sub.B1 " and "N.sub.B2 ", respectively. A drain of P-channel transistor 13 is connected to a drain of N-channel transistor 16 at output node 101 for providing an output signal labeled "V.sub.OUTM " to a load which includes load capacitance 24. In the second symmetrical half, P-channel transistor 23 has a source connected to relatively constant current source 21, and receives an input signal labeled "V.sub.INM ". A drain of P-channel transistor 23 is connected between N-channel transistors 18 and 19 at internal node 104. P-channel transistors 14 and 15 are series connected, and receive bias voltages P.sub.B1 and P.sub.B2, respectively. Cascode connected N-channel transistors 18 and 19 receives bias voltages N.sub.B1 and N.sub.B2, respectively. A drain of P-channel transistor 15 is connected to a drain of N-channel transistor 18 at output node 102 for providing an output signal labeled "V.sub.OUTP " to a load which includes load capacitance 25. Input signals V.sub.INP and V.sub.INM are analog level differential input signals.
Prior art cascode differential amplifier 10 is commonly used as a voltage gain stage in a multi-stage operational amplifier (not shown). In addition, cascode differential amplifier 10 may be used as a building block for switched-capacitor integrators. In operation, prior art cascode differential amplifier 10 receives relatively weak, analog level, differential input signals V.sub.INP and V.sub.INM, and in response, provides amplified differential output signals V.sub.OUTM and V.sub.OUTP. Output nodes 101 and 102 are high impedance nodes, where a small change in current produces a large change in voltage. The dominant poles of cascode differential amplifier 10 are located at output nodes 101 and 102 and are determined by the capacitance of load capacitors 24 and 25.
Each of transistors 12-19, 22, and 23 are biased into the saturation region of operation. P-channel transistors 22 and 23 form a differential pair having their sources connected to current source 21, for receiving input signals V.sub.INP and V.sub.INM. P-channel transistors 22 and 23 are connected as common-source amplifiers, and function to steer a current provided by current source 21 for amplifying the voltage of input signals V.sub.INP and V.sub.INM. Input signal V.sub.INP is amplified in a phase opposite that of input signal V.sub.INM. N-channel transistors 16 and 18 function as common-drain amplifiers and provide a second amplification of input signals V.sub.INP and V.sub.INM with zero phase shift. P-channel transistors 14 and 15, and N-channel transistors 18 and 19 are connected as cascode pairs, respectively, and function to reduce the conductance at output node 102. Likewise, P-channel transistors 12 and 13, and N-channel transistors 16 and 17 are connected as cascode pairs, respectively, and reduce the conductance at output node 101. The lower output conductance results in relatively high voltage gain at output: nodes 101 and 102. The conductance of P-channel transistors 22 and 23, in conjunction with the signal current division that occurs at nodes 103 and 104 also impacts the voltage gain of cascode differential amplifier 10. The signal current division is determined by the drain-source conductances of P-channel transistor 23 and N-channel transistor 19 in the second symmetrical hall and by P-channel transistor 22 and N-channel transistor 17 in the first symmetrical half, as well as the conductance into the drain of N-channel transistors 16 and 18.
A problem with prior art cascode differential amplifier 10 is that a second pole exists at each of nodes 103 and 104. The second pole decreases the phase margin of prior art cascode differential amplifier 10 and may cause increased small signal settling time. Note that the phase margin is equal to 180 degrees minus the phase of an amplifier, when the amplifier is operating at the amplifier's unity gain frequency. In order for amplifier 10 to be useful, a phase margin of about 45 degrees or more is needed. The stability of prior art cascode differential amplifier 10 is related to the phase margin. Generally, increasing the phase margin results in a corresponding increase in stability.
For many applications, prior art differential amplifier 10 functions satisfactorily; however, in high frequency applications, the unity gain frequency may approach the position of the second pole, causing phase margin degradation. To allow operation at higher frequencies, the unity gain frequency of the second pole may be increased, by increasing the conductance and decreasing the capacitance at nodes 103 and 104. However, this may cause an undesirable reduction in voltage gain.